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W39F010 128k 8 cmos flash memory publication release date: december 26, 2005 - 1 - revision a4 table of contents- 1. general des cription ......................................................................................................... 3 2. features ....................................................................................................................... .......... 3 3. pin configura tions ............................................................................................................ 4 4. block di agram .................................................................................................................. .... 5 5. pin descri ption................................................................................................................ ..... 6 6. functional des cription ................................................................................................... 7 6.1 device bus o peratio n..................................................................................................... 7 6.1.1 read m ode ...............................................................................................................7 6.1.2 write m ode ...............................................................................................................7 6.1.3 standby m ode ..........................................................................................................7 6.1.4 output disabl e mode ................................................................................................7 6.2 data prot ection ............................................................................................................... 7 6.3 boot block o peratio n...................................................................................................... 8 6.3.1 low vdd i nhibit ........................................................................................................8 6.3.2 write pulse "glitch " protec tion .................................................................................8 6.3.3 logical inhi bit............................................................................................................8 6.3.4 power-up write inhibit ..............................................................................................8 6.4 command defi nitions ..................................................................................................... 8 6.4.1 read comm and .......................................................................................................9 6.4.2 auto-select command ..............................................................................................9 6.4.3 byte program comm and ..........................................................................................9 6.4.4 chip erase command ............................................................................................10 6.4.5 page erase command ...........................................................................................10 6.5 write operati on status ................................................................................................. 10 6.5.1 dq7: data polling ...................................................................................................10 6.5.2 dq6: toggl e bit ......................................................................................................11 7. table of operat ing mode s ............................................................................................ 12 7.1 device bus o perati ons ................................................................................................. 12 7.2 command defi nitions ................................................................................................... 12 7.3 embedded programming algorit hm ............................................................................. 14 7.4 embedded erase al gorithm .......................................................................................... 15 7.5 embedded #data polli ng algorit hm.............................................................................. 16 7.6 boot block lockout e nable flow chart ........................................................................ 17 7.7 software product identification and boot bl ock lockout detecti on flow chart........... 18
W39F010 - 2 - 8. dc character istics .......................................................................................................... 19 8.1 absolute maxi mum rati ngs .......................................................................................... 19 8.2 dc operating char acterist ics....................................................................................... 19 8.3 pin capacit ance ............................................................................................................ 19 9. ac character istics .......................................................................................................... 20 9.1 ac test c onditions ....................................................................................................... 20 9.2 ac test load and wavefo rm ....................................................................................... 20 9.3 read cycle timing paramete rs.................................................................................... 21 9.4 write cycle timi ng parame ters .................................................................................... 21 9.5 power-up ti ming........................................................................................................... 22 9.6 data polling and toggle bi t timing para meters .......................................................... 22 10. timing w aveforms ............................................................................................................. 23 10.1 read cycle timi ng diagr am......................................................................................... 23 10.2 #we controlled command write cycle timi ng diagr am............................................. 23 10.3 #ce controlled command write cycle timi ng diagr am.............................................. 24 10.4 chip erase ti ming diagr am ......................................................................................... 24 10.5 page erase timi ng diagr am ........................................................................................ 25 10.6 #data polling ti ming diagr am .................................................................................... 25 10.7 toggle bit timi ng diagr am ........................................................................................... 26 11. ordering info rmation .................................................................................................... 27 12. how to read the top marking...................................................................................... 28 13. package dime nsions ......................................................................................................... 29 13.1 32-pin p- dip ................................................................................................................. 29 13.2 32-pin tsop (8 x 20 mm)............................................................................................. 30 13.3 32-pin pl cc ................................................................................................................. 31 13.4 32-pin stsop (8 x 14 mm) .......................................................................................... 31 14. version hi story ................................................................................................................ .32
W39F010 publication release date: december 26, 2005 - 3 - revision a4 1. general description the W39F010 is a 1mbit, 5-volt only cmos flash memory organized as 128k 8 bits. for flexible erase capability, the 1mbits of data are divided into 32 small even pages with 4 kbytes. the byte-wide ( 8) data appears on dq7 ? dq0. the device can be programmed and erased in-system with a standard 5v power supply. a 12-volt v pp is not required. the unique cell architecture of the W39F010 results in fast program/erase operations with ex tremely low current consumption (compared to other comparable 5-volt flash memory products). the device can also be programmed and erased by using standard eprom programmers. 2. features y single 5-volt operations ? 5-volt read ? 5-volt erase ? 5-volt program y fast program operation: ? byte-by-byte programming: 50 s (max.) y fast erase operation: ? chip erase cycle time: 100 ms (max.) ? page erase cycle time: 25 ms (max.) y read access time: 70/90 ns y 32 even pages with 4k bytes y any individual page can be erased y hardware protection: ? optional 16k byte top/bottom boot block with lockout protection y flexible 4k-page size can be used as parameter blocks y typical program/erase cycles: ? 1k/10k y twenty-year data retention y low power consumption ? active current: 15 ma (typ.) ? standby current: 15 a (typ.) y end of program detection ? software method: toggle bit/data polling y ttl compatible i/o y jedec standard byte-wide pinouts y available packages: 32-pin 600 mil dip, 32-pin plcc, 32- pin stsop (8 x 14 mm) and 32- pin tsop
W39F010 publication release date: december 26, 2005 - 4 - revision a4 3. pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dq0 dq1 dq2 vss a7 a6 a5 a4 a3 a2 a1 a0 nc a16 a15 a12 v #we a14 a13 a8 a9 a11 #oe a10 #ce dq7 dq6 dq5 dq4 dq3 dd 32-pin dip 5 6 7 9 10 11 12 13 a7 a6 a5 a4 a3 a2 a1 a0 dq0 29 28 27 26 25 24 23 22 21 30 31 32 1 2 3 4 8 20 19 18 17 16 15 14 d q 1 d q 2 v s s d q 3 d q 4 d q 5 d q 6 a14 a13 a8 a9 a11 #oe a10 #ce dq7 a 1 2 a 1 6 n c v d d # w e a 1 5 32-pin plcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a3 a2 a1 a0 dq0 dq1 dq2 vss #oe a10 #ce dq7 dq6 dq5 dq4 dq3 32-pin tsop a15 a12 a7 a6 a5 a4 v #we a14 a13 a8 dd a11 a9 nc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 nc n c nc
W39F010 publication release date: december 26, 2005 - 5 - revision a4 4. block diagram dq 0 - dq 7 a 0 - a 16 data latch input / output buffers chip enable output enable logic y-mux / sensing array y-decode x-decode a d d r e s s l a t c h state control command register #ce #we #oe vdd vss vdd detect timer erase voltage generator program voltage generator
W39F010 - 6 - 5. pin description symbol pin name a0 ? a16 address inputs dq0 ? dq7 data inputs/outputs #ce chip enable #oe output enable #we write enable v dd power supply v ss ground nc no connections
W39F010 publication release date: december 26, 2005 - 7 - revision a4 6. functional description 6.1 device bus operation 6.1.1 read mode the read operation of the W39F010 is controlled by #ce and #oe, both of which have to be low for the host to obtain data from the outputs. #ce is used for device selection. when #ce is high, the chip is de-selected and only standby power will be consumed. #oe is the output control and is used to gate data from the output pins. the data bus is in hi gh impedance state when either #ce or #oe is high. refer to the timing waveforms for further details. 6.1.2 write mode device erasure and programming are accomplished vi a the command register. the contents of the register serve as inputs to the in ternal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addre ssable memory location. the register is a latch used to store the commands, along with the addr ess and data information needed to execute the command. the command register is written to bring #w e to logic low state, while #ce is at logic low state and #oe is at logic high state. addresses are latched on the falling edge of #we or #ce, whichever happens later; while data is latched on the rising edge of #we or #ce, whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the er ase/programming waveforms for specific timing parameters. 6.1.3 standby mode there are two ways to implement the standby m ode on the W39F010 device, both using the #ce pin. a cmos standby mode is achieved with the #ce input held at v dd 0.5v. under this condition the current is typically reduced to less than 50 a. a ttl standby mode is achieved with the #ce pin held at v ih . under this condition the current is typically reduced to 2 ma. in the standby mode the outputs are in the hi gh impedance state, independent of the #oe input. 6.1.4 output disable mode with the #oe input at a logic high level (v ih ), output from the device is disabled. this will cause the output pins to be in a high impedance state. 6.2 data protection the W39F010 is designed to offer protection against acci dental erasure or programming caused by spurious system level signals that may exist dur ing power transitions. during power up the device automatically resets the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents onl y occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v dd power-up and power-down transitions or system noise.
W39F010 - 8 - 6.3 boot block operation there are two alternatives to set the boot block. t he 16k-byte in the top/bottom location of this device can be locked as boot block, which can be used to stor e boot codes. it is located in the last 16k bytes or first 16k bytes of the memory with the address range from 1c000(hex) to 1ffff(hex) for top location or 00000(hex) to 03fff(hex) for bottom location. see command codes for boot block lockout enable for t he specific code. once this feature is set the data for the designated block cannot be erased or pr ogrammed (programming lockout), other memory locations can be changed by the regular programming method. in order to detect whether the boot block feature is set on the first/last 16k-byte block or not, users can perform software command sequence: enter the product identification mode (see command codes for identification/boot bl ock lockout detection for specific code), and then read from address 0002(hex) for first(bottom) location or 1fff2(hex) fo r last(top) location. if the dq0/dq1 of output data is "1," the 16kbytes boot block programming lock out feature will be activat ed; if the dq0/dq1 of output data is "0," the lockout feature will be i nactivated and the block can be erased/programmed. to return to normal operation, perform a three- byte command sequence (or an alternate single-byte command) to exit the identification mode. fo r the specific code, see command codes for identification/boot blo ck lockout detection. 6.3.1 low v dd inhibit to avoid initiation of a write cycle during v dd power-up and power-down, the W39F010 locks out when v dd < 2.0v (see dc characteristics section fo r voltages). the write and read operations are inhibited when v dd is less than 2.0v typical. the W39F010 ignores all write and read operations until v dd > 2,0v. the user must ensure that the control pins are in the correct logic state when v dd > 2.0v to prevent unintentional writes. 6.3.2 write pulse "glitch" protection noise pulses of less than 10 ns (typical) on #oe, #ce, or #we will not initiate a write cycle. 6.3.3 logical inhibit writing is inhibited by holding any one of #oe = v il , #ce = v ih , or #we = v ih . to initiate a write cycle #ce and #we must be a logical zero while #oe is a logical one. 6.3.4 power-up write inhibit power-up of the device with #we = #ce = v il and #oe = v ih will not accept commands on the rising edge of #we except 5ms delay (see the power up timi ng in ac characteristics). the internal state machine is automatically reset to the read mode on power-up. 6.4 command definitions device operations are selected by writing s pecific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "command definitions " defines the valid register command sequences.
W39F010 publication release date: december 26, 2005 - 9 - revision a4 6.4.1 read command the device will automatically power-up in the read state. in this case, a command sequence is not required to read data. standard microprocessor read cycl es will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. the device will automatically returns to r ead state after completing an embedded program or embedded erase algorithm. refer to the ac read characteristics and wave forms for the specific timing parameters. 6.4.2 auto-select command flash memories are intended for use in applications where the local cpu can alter memory contents. as such, manufacture and device codes must be acce ssible while the device resides in the target system. the device contains an auto-select command operat ion to supplement traditional prom programming methodology. the operation is initiated by writ ing the auto-select command sequence into the command register. following the command write, a read cycle from address xx00h retrieves the manufacture code of dah. a read cycle from address xx01h returns the device code (W39F010 = a1). to terminate the operation, it is necessary to write the auto-select exit command sequence into the register. 6.4.3 byte program command the device is programmed on a byte-by-byte basis. programming is a four-bus-cycle operation. the program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. the program address and data are wr itten next, which in turn initiate the embedded program algorithm. addresses are latched on t he falling edge of #ce or #we, whichever happens later and the data is latched on the rising edge of #ce or #we, whichever happens first. the rising edge of #ce or #we (whichever happens first) begins programming using the embedded program algorithm. upon executing the algorit hm, the system is not required to provide further controls or timings. the device will automatically provide adequat e internally generated program pulses and verify the programmed cell margin. the automatic programming operation is comple ted when the data on dq7 (also used as data polling) is equivalent to the data written to this bi t at which time the device returns to the read mode and addresses are no longer latched (see "hardwar e sequence flags"). therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for data polling operations. data polling must be performed at the memory location which is being programmed. any commands written to the chip during t he embedded program algorithm will be ignored. if a hardware reset occurs during the programming operati on, the data at that particular location will be corrupted. programming is allowed in any sequence and across page boundaries. beware that a data "0" cannot be programmed back to a "1". attempting to program 0 back to 1, the toggle bit will stop toggling. only erase operations can c onvert "0"s to "1"s. refer to the programming command flow chart us ing typical command strings and bus operations.
W39F010 - 10 - 6.4.4 chip erase command chip erase is a six-bus-cycle operation. there are two "unlock" write cycles , followed by writing the "set-up" command. two more "unl ock" write cycles are asserted, followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devic e will automatically erase and verify the entire memory for an all one data pattern. the er ase is performed sequentially on each pages at the same time (see "feature"). the syst em is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last #we pulse in the command sequence and terminates when the data on dq7 is "1" at whic h time the device returns to read the mode. refer to the erase command flow chart usi ng typical command strings and bus operations. 6.4.5 page erase command page erase is a six-bus cycles operation. there are two "unlock" write cycles , followed by writing the "set-up" command. two more "unlock" write cy cles then follows by the page erase command. the page address (any address location within the desired page) is latched on the falling edge of #we, while the command (50h) is latched on the rising edge of #we. page erase does not require the user to program t he device prior to erase. when erasing a page, the remaining unselected pages are not affected. the syst em is not required to provide any controls or timings during these operations. the automatic page erase begins after the erase comm and is completed, right from the rising edge of the #we pulse for the last page erase command pul se and terminates when the data on dq7, data polling, is "1" at which time the device returns to the read mode. data polling must be performed at an address within any of the pages being erased. refer to the erase command flow chart usi ng typical command strings and bus operations. 6.5 write operation status 6.5.1 dq7: data polling the W39F010 device features data polling as a me thod to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce the complement of the data last written to dq7. upon completi on of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq7. during the embedded erase algorithm, an attempt to read the device will produce a "0" at the dq7 output. upon completion of the embedded erase algorit hm, an attempt to read the device will produce a "1" at the dq7 output. for chip erase, the data polling is valid after t he rising edge of the sixth pulse in the six #we write pulse sequences. for page erase, the data polling is valid after the last rising edge of the page erase #we pulse. data polling must be performed at addr esses within any of the pages being erased. otherwise, the status may not be valid.
W39F010 publication release date: december 26, 2005 - 11 - revision a4 just prior to the completion of embedded algor ithm operations dq7 may change asynchronously while the output enable (#oe) is asserted low. this m eans that the device is dr iving status information on dq7 at one instant of time and then that byte s valid data at the next instant of time. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operations and dq 7 has a valid data, the data outputs on dq0? dq6 may be still invalid. the valid data on dq0 ? dq7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm, or page erase time -out (see "command definitions"). 6.5.2 dq6: toggle bit the W39F010 also features the "toggle bit" as a me thod to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (#oe toggling) data from the device at any address will result in dq6 toggling between one and zero. once the embedded program or erase algorithm cycle is comp leted, dq6 will stop toggling and valid data will be read on the next successive attempt. during programming, the toggle bit is valid after the rising edge of the fourth #we pulse in the four write pulse sequence. for chip erase, the toggle bit is valid after the rising edge of the sixth #we pulse in the six write pulse sequence. for page erase, the toggle bit is valid after the last rising edge of the page erase #we pulse. the toggle bit is active during the page erase time-out. either #ce or #oe toggling will cause dq6 to toggle.
W39F010 - 12 - 7. table of operating modes 7.1 device bus operations pin mode #ce #oe #we dq0 ? dq7 read v il v il v ih dout write v il v ih v il din standby v ih x x high z x v il x high z/ dout write inhibit x x v ih high z/ dout output disable v il v ih v ih high z 7.2 command definitions command no. of 1st cycle 2nd cycle 3rd cycle 4 th cycle 5th cycle 6th cycle 7th cycle description cycles addr. (1) data addr. data addr. data addr. data addr. data addr. data addr. data read 1 a in d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 page erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 pa (3) 50 byte program 4 5555 aa 2aaa 55 5555 a0 a in d in top boot block lockout ?16kbyte 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 70 1ffff xx (4) bottom boot block lockout - 16kbyte 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 70 00000 xx (4) product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 notes : 1. address format: a14 ? a0 (hex); data format: dq7 ? dq0 (hex) 2. either one of the two product id exit commands can be used. 3. pa: page address
W39F010 publication release date: december 26, 2005 - 13 - revision a4 pa = 1fxxxh for page 31 pa = 0fxxxh for page 15 pa = 1exxxh for page 30 pa = 0exxxh for page 14 pa = 1dxxxh for page 29 pa = 0dxxxh for page 13 pa = 1cxxxh for page 28 pa = 0cxxxh for page 12 pa = 1bxxxh for page 27 pa = 0bxxxh for page 11 pa = 1axxxh for page 26 pa = 0axxxh for page 10 pa = 19xxxh for page 25 pa = 09xxxh for page 9 pa = 18xxxh for page 24 pa = 08xxxh for page 8 pa = 17xxxh for page 23 pa = 07xxxh for page 7 pa = 16xxxh for page 22 pa = 06xxxh for page 6 pa = 15xxxh for page 21 pa = 05xxxh for page 5 pa = 14xxxh for page 20 pa = 04xxxh for page 4 pa = 13xxxh for page 19 pa = 03xxxh for page 3 pa = 12xxxh for page 18 pa = 02xxxh for page 2 pa = 11xxxh for page 17 pa = 01xxxh for page 1 pa = 10xxxh for page 16 pa = 00xxxh for page 0 4. xx: don't care
W39F010 - 14 - 7.3 embedded programming algorithm start write program command sequence (see below) increment address programming completed 5555h/aah 2aaah/55h 5555h/a0h program address/program data #data polling/ toggle bit last address ? no yes program command sequence (address/command): pause t bp
W39F010 publication release date: december 26, 2005 - 15 - revision a4 7.4 embedded erase algorithm start write erase command sequence (see below) erasure completed #data polling or toggle bit successfully completed 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h 5555h/10h chip erase command sequence (address/command): 5555h/aah 5555h/aah 2aaah/55h 2aaah/55h 5555h/80h page address/50h individual page erase (address/command): command sequence pause t ec /t pec
W39F010 - 16 - 7.5 embedded #data polling algorithm start read byte (dq0 - dq7) address = va pass dq7 = data ? yes no va = byte address for programming = any of the page addresses within the page being erased during page erase operation =any of the device addresses being erased during chip operation embedded toggle bit algorithm start read byte (dq0 - dq7) address = don't care dq6 = toggle ? yes no pass
W39F010 publication release date: december 26, 2005 - 17 - revision a4 7.6 boot block lockout enable flow chart boot block lockout feature set flow load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 70 to address 5555 pause t exit 70 to lock 16k boot block load data xx to address 1ffff/0 1ffff(xx) to lock top boot block 00000(xx) to lock bottom boot block bp
W39F010 - 18 - 7.7 software product identification and boot block lockout detection flow chart product identification entry (1) load data 55 to address 2aaa load data 90 to address 5555 pause 10 s product identification and boot block lockout detection mode (3) read address = 0000 data = da read address = 0001 read address=02/1fff2 for bottom/top data: in dq1="1" or "0" for 16k boot block (4) product identification exit(6) load data 55 to address 2aaa load data f0 to address 5555 normal mode (5) (2) (2) load data aa to address 5555 load data aa to address 5555 pause 10 s data = a1 notes for software product identificati on/boot block lockout detection: (1) data format: dq7 ? dq0 (hex); address format: a14 ? a0 (hex) (2) a1 ? a16 = v il ; manufacture code is read for a0 = v il ; device code is read for a0 = v ih . (3) the device does not remain in identification and boot block lockout detection mode if power down. (4) if the output data in dq0 or dq1= " 1 " the boot block pr ogramming lockout feature is activated; if the output data in dq0 or dq1= " 0 ," the lockout feature is i nactivated and the matched boot block can be programmed. (5) the device returns to standard operation mode. (6) optional 1-byte cycle (write f0 hex at xxxx address) can be used to exit the product identification/boot block lockout detection.
W39F010 publication release date: december 26, 2005 - 19 - revision a4 8. dc characteristics 8.1 absolute maximum ratings parameter rating unit power supply voltage to v ss potential -2.0 to +7.0 v operating temperature 0 to +70 c storage temperature -65 to +125 c voltage on any pin to ground potential except a9 -2.0 to +7.0 v voltage on a9 pin to ground potential -2.0 to +13.0 v note : exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. 8.2 dc operating characteristics (v dd = 5v 0.5v, v ss = 0v, t a = 0 to 70 c) limits parameter sym. test conditions min. typ. max. unit power supply current i dd #ce = #oe = v il , #we = v ih , all dqs open address inputs = v il /v ih , at f = 5 mhz - 15 30 ma standby v dd current (ttl input) i sb 1 #ce = v ih , all dqs open other inputs = v il /v ih - 1 2 ma standby v dd current (cmos input) i sb 2 #ce = v dd -0.3v, all dqs open other inputs = v dd -0.3v/ v ss - 15 50 a input leakage current i li v in = v ss to v dd - - 1 a output leakage current i lo v out = v ss to v dd - - 1 a input low voltage v il - -0.3 - 0.8 v input high voltage v ih - 2.0 - v dd +0.5 v output low voltage v ol i ol = 2.1 ma - - 0.45 v output high voltage v oh i oh = -0.4 ma 2.4 - - v 8.3 pin capacitance (v dd = 5v, t a = 25 c, f = 1 mhz) parameter symbol conditions typ. max. unit input capacitance c in v in = 0v 6 8 pf output capacitance c out v out = 0v 10 12 pf
W39F010 - 20 - 9. ac characteristics 9.1 ac test conditions parameter conditions input pulse levels 0v to 3v input rise/fall time <5 ns input/output timing level 1.5v/1.5v output load 1 ttl gate and c l = 30 pf 9.2 ac test load and waveform +5v 1.8k 1.3k d out 30 pf (including jig and scope) input 3v 0v test point test point 1.5v 1.5v output
W39F010 publication release date: december 26, 2005 - 21 - revision a4 ac characteristics, continued 9.3 read cycle timing parameters (v dd = 5v 0.5v, v ss = 0v, t a = 0 to 70 c) W39F010-70 W39F010-90 parameter symbol min. max. min. max. unit read cycle time t rc 70 - 90 - ns chip enable access time t ce - 70 - 90 ns address access time t aa - 70 - 90 ns output enable access time t oe - 35 - 45 ns #ce low to active output t clz 0 - 0 - ns #oe low to active output t olz 0 - 0 - ns #ce high to high-z output t chz - 25 - 25 ns #oe high to high-z output t ohz - 25 - 25 ns output hold from address change t oh 0 - 0 - ns 9.4 write cycle timing parameters parameter symbol min. typ. max. unit address setup time t as 0 - - ns address hold time t ah 40 - - ns #we and #ce setup time t cs 0 - - ns #we and #ce hold time t ch 0 - - ns #oe high setup time t oes 0 - - ns #oe high hold time t oeh 0 - - ns #ce pulse width t cp 100 - - ns #we pulse width t wp 100 - - ns #we high width t wph 100 - - ns data setup time t ds 40 - - ns data hold time t dh 10 - - ns byte programming time t bp - 35 50 s chip erase cycle time t ec - 50 100 ms page erase cycle time t ep - 12.5 25 ms note : all ac timing signals observe the following guideli nes for determining setup and hold times: (a) high level signal's reference level is v ih and (b) low level signal's reference level is v il .
W39F010 - 22 - ac characteristics, continued 9.5 power-up timing parameter symbol typical unit power-up to read operation t pu . read 100 s power-up to write operation t pu . write 5 ms 9.6 data polling and toggle bit timing parameters W39F010-70 W39F010-90 parameter sym. min. max. min. max. unit #oe to data polling output delay t oep - 35 - 45 ns #ce to data polling output delay t cep - 70 - 90 ns #oe to toggle bit output delay t oet - 35 - 45 ns #ce to toggle bit output delay t cet - 70 - 90 ns
W39F010 publication release date: december 26, 2005 - 23 - revision a4 10. timing waveforms 10.1 read cycle timing diagram address a16-0 dq7-0 data valid data valid high-z #ce #oe #we t rc v ih t clz t olz t oe t ce t oh t aa t chz t ohz high-z 10.2 #we controlled command write cycle timing diagram address a16-0 dq7-0 data valid #ce #oe #we t as t cs t oes t ah t ch t oeh t wph t wp t ds t dh
W39F010 - 24 - timing waveforms, continued 10.3 #ce controlled command write cycle timing diagram high z data valid #ce #oe #we dq7-0 t as t ah t cph t oeh t dh t ds t cp t oes address a16-0 10.4 chip erase timing diagram sb2 sb1 sb0 address a16-0 dq7-0 #ce #oe #we sb3 sb4 sb5 internal erase starts six-byte code for 5v-only software chip erase t wp t wph t ec 5555 2aaa 5555 5555 2aaa 5555 aa 55 80 aa 55 10
W39F010 publication release date: december 26, 2005 - 25 - revision a4 timing waveforms, continued 10.5 page erase timing diagram sb2 sb1 sb0 address a16-0 dq7-0 #ce #oe #we sb3 sb4 sb5 internal erase starts six-byte commands for 5v-onl y page erase t wp t wph t ep 5555 2aaa 5555 5555 2aaa pa aa 55 80 aa 55 50 pa = page address please refer to page 9 for detail informati o 10.6 #data polling timing diagram address a16-0 dq7 #we #oe #ce x x x x t cep t oeh t oep t oes t ec t bp or an an an an
W39F010 - 26 - timing waveforms, continued 10.7 toggle bit timing diagram address a16-0 dq6 #ce #oe #we t oeh t oes t bp or t ec
W39F010 publication release date: december 26, 2005 - 27 - revision a4 11. ordering information part no. access time (ns) power supply current max. (ma) standby vdd current max. (ma) package cycle W39F010-70b 70 30 2 32-pin dip 10k W39F010-90b 90 30 2 32-pin dip 10k W39F010t-70b 70 30 2 32-pin tsop (8 mm x 20 mm) 10k W39F010t-90b 90 30 2 32-pin tsop (8 mm x 20 mm) 10k W39F010q-70b 70 30 2 32-pin stsop (8 mm x 14 mm) 10k W39F010q-90b 90 30 2 32-pin stsop (8 mm x 14 mm) 10k W39F010p-70b 70 30 2 32-pin plcc 10k W39F010p-90b 90 30 2 32-pin plcc 10k W39F010p-70z 70 30 2 32-pin plcc (lead free) 10k W39F010p-90z 90 30 2 32-pin plcc (lead free) 10k notes : 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
W39F010 - 28 - 12. how to read the top marking example: the top marking of 32-pin plcc W39F010p-70 1 st line: winbond logo 2 nd line: the part number: W39F010p-70 3 rd line: the lot number 4 th line: the tracking code: 149 o b sa 149: packages made in '01, week 49 o: assembly house id : a means ase, o means ose, ...etc. b: ic revision; a means version a, b means version b, ...etc. sa: process code W39F010p-70 2138977a-a12 149obsa
W39F010 publication release date: december 26, 2005 - 29 - revision a4 13. package dimensions 13.1 32-pin p-dip 1.dimensions d max. & s include mold fl a tie bar burrs. 2.dimension e1 does not include interlea 3.dimensions d & e1 include mold mism a are determined at the mold parting li n 6.general appearance spec. should be b a final visual inspection spec . . 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 015 0.085 2.16 0.650 0.630 16.00 16.51 protrusion/intrusion. 4.dimension b1 does not include dam 5.controlling dimension: inche s 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17
W39F010 - 30 - 13.2 32-pin tsop (8 x 20 mm) a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d note: controlling dimension: millimeters dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 3 5 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 3 5 dimension in mm __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __
W39F010 publication release date: december 26, 2005 - 31 - revision a4 package dimensions, continued 13.3 32-pin plcc l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 notes: 1. dimensions d & e do not include interlead flash. 2. dimension b1 does not include dambar protrusion/intrusion. 3. controlling dimension: inches. 4. general appearance spec. should be based on final visual inspection sepc. symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 h d g e 12.45 12.95 13.46 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 0.020 0.140 1.12 1.42 0.044 0.056 0 10 10 0 0.10 2.41 13.4 32-pin stsop (8 x 14 mm) min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 0.50 0.00 0 0.22 0.27 ----- 0.21 12.40 8.00 14.00 0.50 0.60 0.70 0.80 0.10 35 0.047 0.006 0.041 0.040 0.035 0.007 0.009 0.010 0.004 ----- 0.008 0.488 0.315 0.551 0.020 0.020 0.024 0.028 0.031 0.000 0.004 035 0.002 a a b c d e e l l y 1 1 2 a h d dimension in mm a a a 2 1 l l 1 y e h d d c b e
W39F010 - 32 - 14. version history version date page description a1 dec. 2000 - initial issued 1, 23 add cycle of 1k 1 change active current from 10 to15ma (typ.) change standby current from 20 to15 a (typ.) 4 modify low vdd inhibit 10, 11, 12 delete old flow chart and add embedded algorithm 10 remove block erase from the embedded erase algorithm 11 correct embedded #data polling algorithm 16 change idd from 10/20 ma to15/30 ma (typ./max.) change isb2 from 20/50 a to15/50 a (typ./max.) 1, 23 rename tsop (8 x 14 mm) as stsop (8 x 14 mm) a2 june 17, 2002 24 add how to read the top marking a3 april 15, 2005 27 add important notice a4 december 26, 2005 27 add 32-pin plcc lead free part
W39F010 publication release date: december 26, 2005 - 33 - revision a4 important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales.

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